1. Field of the Invention
The present invention relates to an array substrate and a method for manufacturing the same, and more particularly, to an array substrate and a method for manufacturing the same in order to reduce flickers of frames.
2. Description of Related Art
Cathode ray tube televisions are now virtually obsolete due to their bulkiness and have been replaced by thin and light display devices, such as liquid crystal displays (LCDs). Among LCDs, thin film transistor liquid crystal displays (TFT-LCDs) are of particular interest to R&D in this field.
In TFT-LCDs, the response rate of liquid crystal (LC) is one of directions for study. In this kind of LCDs, each pixel is electrically connected with a TFT as a switch element. In a determined period, the TFT inputs electricity required for the pixel, and the input electricity is maintained until the next input of electricity required for the next scanning. Generally, the capacitance of the LC is not large. It is difficult to maintain original input electricity only by the capacitance of the LC until the next input of electricity required for the next scanning. Hence, a storage capacitor (Cs) is required to connect with the TFT of the pixel in parallel so as to increase the capacitance maintaining the electricity. In general, the Cs is disposed on the gate or on the common electrode.
However, the above-mentioned parallel disposition of the storage capacitor line and the gate electrode line results in a crosstalk effect generated by the data line due to the storage capacitor line. Therefore, there is a layout of the storage capacitor line and the data line disposed in parallel to reduce the crosstalk effect. As shown in FIG. 1, a pixel 10 is enclosed by two neighbor data lines 11 and two neighbor scan lines 12, and has a TFT 13 serving as a switch element. Near the switch element, the data line 11 is interlaced with the scan line 12. A storage capacitor line 14 is disposed in parallel to the data line 11, and is used for formation and connection of storage capacitance of every pixel 10. A pixel electrode 15 crosses over two data lines 11 and two scan lines 12. However, in the LCDs having the storage capacitor lines 14 in parallel to the data lines 11, while the TFT 13 is turned off, a kickback voltage (ΔVp) toward the pixel electrode 15 is generated by the scan line 12 due to a parasitic capacitance. An equation is as follows:
      Δ    ⁢                  ⁢    Vp    =            (              Vgh        -        Vgl            ⁢                          )        ⁢                  ⁢          Cgd              Clc        +        Ccs        +        Cgd            wherein Vgh is a voltage of turning on the gate; Vgl is a voltage of turning off the gate; Clc is a capacitance of the LC; Ccs is a storage capacitance; and Cgd is a parasitic capacitance. If the parasitic capacitance is large, the kickback voltage (ΔVp) is large. Due to the kickback voltage (ΔVp), a feedthrough voltage under polar changes of the pixel electrode results in the flickers of a frame.